1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of operation modes.
2. Description of the Related Art
Conventionally, as a semiconductor memory device having a plurality operation modes, a SDRAM (Synchronous Dynamic Random Access Memory), for example, has been available. The operation mode in the SDRAM is set by the input of an illegal command (a command that is not a read, write, or refresh command). As the operation mode of the SDRAM, there are, for example, read latency (RL), burst length (BL), partial size (PS), and so on.
RL is an operation mode for setting the number of clocks required from the input of an address to the output of data read from a memory cell. In this mode, three kinds of the numbers of clocks can be set, for, example, 3 clocks, 4 clocks, and 5 clocks. BL is an operation mode for setting a word length at the time of the burst transfer. In this mode, three kinds of the word lengths can be set, for example, 8 words, 16 words, and a continuous. PS is an operation mode for setting the size of an area for partial refresh. The partial refresh is an operation in which, when, for example, most of memory cells of the SDRAM are not used for a certain period of time and only part of data are required to be retained, only the area retaining the data is refreshed. With this operation, the refresh areas are lessened to allow reduction in power consumption.
In an asynchronous DRAM, only an operation mode such as PS not involved in the burst transfer is set (hereinafter, referred to as mode setting) based on the combination of a plurality of legal commands. An example of the combination of the legal commands for the mode setting is such that write to the same addresses (in this case, all the addresses H) is executed continuously four times after one read, and re-read is not normally executed. Such a combination is a combination that is not normally executed. Address data (=to be mode designation data) are fetched to a mode register that stores the mode designation data for determining an operation mode, at the time of the final read. This timing is the same timing at which address data are fetched in a normal read operation.
A semiconductor memory device having, for example, the following configuration has been disclosed (for example, Japanese Patent Application Laid-open No. 11-45571). In this semiconductor memory device, an internal clock signal generating circuit has a clock width adjusting circuit for adjusting a pulse width of a first internal clock signal in response to the timing of a second internal clock signal, a first latch circuit sets the hold time, and a second latch circuit sets the setup time. In this manner, an internal window width of each command control signal is made larger than a conventional one to shorten the external setup time and the hold time. Consequently, a stable command control signal can be inputted in a high-frequency operation.
Further, a page-mode mask ROM, for example, having the following configuration has been disclosed (for example, Japanese Patent Application Laid-open No. 9-129824). In this page-mode mask ROM, a memory element includes: a Y pre-decoder that pre-decodes a Y address when receiving the control by an enable signal that is formed in response to address transition; a sensing/amplifying means for sensing/amplifying data read from the Y decoder controlled by the enable signal; a first latch means for latching an output of the sensing/amplifying means; a 2-stage latch means constituted of a switching element for transmitting data latched by the first latch means to a second latch means in response to an address transition pulse; and a control signal generating means for generating an enable signal and a latch signal in response to the address transition, thereby controlling the Y pre-decoder and the sensing/amplifying means to operate at least twice or more. With this configuration, the number of sensors/amplifiers is reduced, which realizes a downsized chip and reduced power consumption.
Here, there has been a demand for setting an operation mode based on the combination of legal commands also in the above-described SDRAM (synchronous DRAM), as in the asynchronous DRAM. However, if the synchronous DRAM is in, for example, a burst operation mode when, for example, RL is to be set based on the combination of the legal commands, RL to which the operation mode is to be switched is set in a mode register in the middle of the final read operation, so that the operation mode is changed. This gives rise to such a problem that the final read operation cannot be finished.